Acorn User: China/Acorn User China CD-ROM (UK) (Disc B)/Acorn User China CD-ROM (UK) (Disc B).bin/STUTTGART/DATABASE/ULTIMATE/a252arm6.txt

Internet Message Format | 1993-08-09 | 11.3 KB

From: [e-mail] (Nicko van Someren)
Subject: New chips from ARM Ltd.
Date: 13 Feb 91 17:55:31 GMT

VLSI, the people who build the ARM2 and ARM3 chips for the chip making end
of Acorn, now ARM Ltd., very queitly announced advanced info about some
of the new ARM chips.

ARM 600 will be very similar to an ARM3 but will have a memory controler
on the chip, based on the MEMC2.

ARM 700 will be the same but also have a RISC FPU on the same slab.
ARM 800 will be as ARM 700 but with a bigger cache.

The article mentioned that they may have a writeback buffer to improve the
performance when writing out to memory.  No indication was given as to what
speed the chips would run at save that it was hoped that they would be faster
than the ARM3 (VLSI rate the ARM3 at 25MHz) and that the ARM800 was far
enough off that it would go even faster.

By the way, the MEMC2 chip is now a VLSI listed part, though all this really
meens is that one day it may get fabricated and when it does you can get
samples from them.  Since they only seem to have small quantities of info.
and it is all said to be provisional I wouldn't hold your breath for a new
machine from Acorn but at least it meens that something will happen one day.

I will post more info when VLSI send me some data sheets...

+-----------------------------------------------------------------------------+
| Nicko van Someren, [e-mail], (44) 223 358707 or (44) 860 498903    |
|       "Go and buy an Aleph One ARM3 card and stop whining!!!"               |
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From: [e-mail] (Dave Jaggar)
Subject: ARM6xx Overview
Summary: ARM6 Architecture Description
Date: 13 Nov 91 10:33:35 GMT

Here's a short description of the ARM6, ARM60 and ARM600 microprocessors,
in response to some general interest. Sorry if it's an ad.

First a little on the ARM Ltd's nomenclature. The first number after
the product name, i.e. the 6 in ARM600 is the architecture specifier.
The number of zeroes indicate how much packaging and extra silicon you
get, so

ARM6 is a macrocell, i.e.  a bunch of transistors that you need to put
in a package (maybe with something else of your own design) before you
can use it.
ARM60 is a chip (comparable to ARM2)
ARM61 is an ARM6 in an ARM2 compatible package, and hard wired in an ARM2
compatible mode.
ARM600 is a chip, utilizing the ARM6 macrocell, and including a 4K cache,
write buffer, and memory management unit (MMU) (comparable to ARM3)

The following assumes you know what an ARM2 and 3 is.

The ARM6 architecture
=====================

    - about 36 000 transistors
    - 30 MHz clock
    - Fully static operation, you can slow the clock down to nothing,
      for as long as you like, and the processor will retain its
      entire state.
    - Very low power consumption
    - 32 bit address and data buses (4 Giga byte address space).
    - 31 32 bit general purpose registers
    - 1 CPSR (Current Processor Status Register) containing 4
      Condition Code (CC) bits, 2 interrupt mask bits, and 5 processor
      mode bits.
    - 5 SPSR (Saved Program Status Registers) on for each major
      processor mode except User.
    - 10 processor modes, User26, IRQ26, FIQ26, Supervisor26, User32,
        IRQ32, FIQ32, Supervisor32, Abort32, and Undefined32.
    - Big and Little Endian operation.
    - The same instruction set as ARM3, except
        - an instruction to move the contents of the CPSR or
          an SPSR to a general register.
        - an instruction to move an immediate constant or the
          contents of a general purpose register to the CPSR
          or an SPSR.
    - Full backwards compatibility modes to 26 bit ARM's via two ways
        - In hardware via external pins.
        - In software via 26 bit processor modes.

Differences between the ARM2 and ARM6 architecture
1) Register 15 now contains a 32 bit Program Counter (PC). The CPSR is
used to hold the CC flags, I and F bits and the processor mode bits.
This means it is no longer possible to save these flags automatically
when a Branch and Link instruction is executed. However when an
exception happens, the CPSR gets copied to the SPSR of the new
(exception) mode and can be restored with a MOVS pc,lr or LDM
Rx,{....,pc}^ upon exit from the exception handler.

2) There are now 10 processor modes.  Four 26 bit compatibility modes
(User, FIQ, IRQ and Supervisor), four corresponding 32 bit modes, and
two new modes, Abort32 and Undefined32.  Abort mode is entered when a
Memory Abort (Prefetch or Data) occurs whilst in a 32 bit mode,
Undefined is entered when the Undefined Instruction exception is taken
whilst in a 32 bit mode.  There is no Address Exception vector (or mode)
in 32 bit modes because 32 bit address are of course legal on an ARM6.
If the processor is hardware configured as 26 bit, there is no way to
get into a 32 bit mode.

3) New instructions for getting at and storing to the CPSR and SPSRs
(called MRS and MSR).

A little about ARM600
=====================

- Uses the ARM6 Macrocell

- About 360 000 transistors

- 20MHz internal clock speed, 12Mhz bus speed.

- Fully static and low power consumption

- The same cache as ARM3 (4Kbyte, 64 way set associative, random
replacement, 4 word lines, write through)

- An 8 deep Write Buffer, with 2 independent addresses, so most write
operations execute in one cycle plus one cycle per register saved, (i.e.
two STR take 4 cycles, an STM with 8 registers takes 9, one STR and an
STM with 7 registers takes 10)

- On chip MMU, including 32 entry Translation Lookaside Buffer (TLB),
with in chip Page Table walking hardware for TLB misses through a two
level page table system.  Memory can be carved up into Segments (1Mbyte)
(not to be confused with Intel style segments), Big Pages (64K) and
Little Pages(4K).  Each page has protection for quarter size subpages.
Any Segment or Page may belong to one of 16 Process Domains, each domain
has its own protection.  Domains allow concurrent garbage collection.

- Support for address alignment faults. Word accesses to non word
addresses may optionally be faulted. Useful for pointer chain following.

- Co-processor interface as on ARM3

Tools
=====

ARM Ltd has available a full complement of support tools, PC and
Unix hosted, including ARM targetted C compiler, ANSI C library,
assembler, linker, debugger, and instruction set emulator.

Dave

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| [e-mail] ([e-mail])              |
| Advanced RISC Machines Ltd, Swaffham Bulbeck, Cambridge CB5 0NA, England |
| Phone: [phone] Extn 210  Fax: [phone]                    |
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From: [e-mail] (Kjetil Bernhard Thomassen)
Subject: GEC-Plessey ARM chips incl. FPA.
Date: 15 Jan 93 05:47:44 GMT

I recently received the 1992/93 shortform catalog from GEC-Plessey
Semiconductors. This has the following ARM chips:

Type                  Max clock freq.       MIPS      Package
P60ARM(4)                  20 MHz             6         GP100
P600ARM(4)                 20 MHz            14         GP160
P610ARM(4)                 20 MHz            14(2)     TQFP144
PFPA10ARM(3)               20 MHz            N/A        HP64

(1) Manufactured under Licence from Advanced RISC Machines Ltd.
(2) Approximate speed, assuming use of DRAM for external memory.
(3) Also requires FPA support code, as some instructions are
    implemented in software.
(4) Software Development Toolkit available.

The ARM60 is just an ARM6 macrocell + whatever is needed to get it going.
The ARM600 is an ARM6 with 4 KB 64-way set-associativ cache, MMU based
on MEMC2, write buffer (8 words, I think) and coprosessor interface.
The ARM610 is essantially an ARM600 without coprosessor interface.
There are a few more differences, and if anyone is interested, I could
post that too.

VLSI Technology manufactures the ARM61 in addition. This is just an
ARM2 built around the ARM6 macrocell.

More information can be obtained from the Local Customer Service
Centre:
UK and Scandinavia: Tel: [phone]
France & BENELUX: Tel: France (1) 64 46 23 45
Germany, Austria & Switzerland: Tel: Germany 089/36 0906-0
Italy: Tel: [phone]
Japan: Tel: [phone]
North Amerika: Integrated Circuits and Microwave Products, CA, USA,
                  Tel: [phone] ITT
               Hybrid Products, NY, USA, Tel: [phone]
South East Asia: Tel: Singapore (65) 3827708
Sweden: Tel: [phone]

I have the data books for the ARM6, ARM60 and ARM610 from GEC-Plessey,
and the full addresses for the Consumer Service Centres.

Please email me if you want the full adresses for the above. I also
have adresses to the world wide distributors.

Kjetil Bernhard Thomassen
[e-mail]




From: [e-mail] (Philip Watson)
Subject: ARM Ltd introduces new RISC Processor
Date: 25 Feb 93 10:44:06 GMT

This extract comes from the latest issue of Electronics Times (25/2/93)

ARM has revealed details of its next generation risc core, the ARM 7.
Apple is among those expected to use it in future generations of handheld
products.

The Arm 7 processor core will use half the power of the existing offering,
the ARM 6, and will be around half the die size. In a full processor design
it should provide 50% to 100% more performance, according to Robin Saxby,
managing director of ARM.

Saxby said a new processor based on the ARM 7 core would be launched in
the second half of the year: "We know the ARM 7 core will work, but the
ARM700 processor with bigger caches we haven't taped out yet."

He said the ARM 6 core in 5v 1um CMOS used 33,500 transistors in 11.1 sq mm
A shrink to 5v 0.8um CMOS reduced the area to 5.4 sq mm, and cut power by
20%. ARM added 2000 transistors to the core to stabilise 3.3v operation,
increasing its area to 5.9 sq mm. Saxby said the ARM 7 core would be
36,000 transistors, and at 3.3v would use half the power of the 5v ARM 6
core.

"The first implementation of the ARM 7 will be in the ARM 700," Saxby added.
"The performance improvement of the ARM 700 over the ARM 610 will be 50 to
100%."

"We have to keep pushing performance up and power consumption down," Saxby
continued.  "Making the right trade-offs is our skill."

Saxby is beginning a concerted move into the Japanese market by opening a
sales and support office on Monday.

"Our remote offices are co-ordination and collaboration offices with
partners," said Saxby.  "We'll also use them to keep our eyes and ears (sic!)
to the ground."  A business development manager has been appointed and trained
by the company.  "One of his jobs will be to communicate with our design
partners."


From: [e-mail]
Date: 3 Jun 93 08:47:13 CDT
Subject: New ARMs

There is an interesting article in Electronics Weekly, June 2nd page 4. Here
are some extracts :-

ARM8 will be a new generation chip with 80-100 Dhrystones - expected to be
available not before 1995." This will not be a successor to the ARM6 or ARM7,
it will be on a different level."

'The successor to the ARM6, the 40-60K Dhrysones ARM7 will be intoduced in the
3rd quarter. Low power processors based on it, the ARM700/710, will be
available at the turn of the year.'

The asynchronous ARM10 is planned for the second half of the decade. This is
based upon a development project ARM is supporting at Manchester University.

ARM6 core has 20-30K Dhrystones.

Article was based on an interview with Robin Saxby.

Ralph Barrett
Fisher Rosemount
Leicester UK